EDI8F32259C 256kx32 sram module 1 EDI8F32259C rev. 1 12/97 eco #9619 the EDI8F32259C is a high speed 8 megabit static ram module organized as 256k words by 32 bits. this module is constructed from eight 256kx4 static rams in soj packages on an epoxy laminate (fr4) board. four chip enables (e?-e3) are used to independently enable the four bytes. reading or writing can be executed on individual bytes or any combination of multiple bytes through proper use of selects. the EDI8F32259C is offered in 72 pin zip/simm package which enables eight megabits of memory to be placed in less than 1.3 square inches of board space. all inputs and outputs are ttl compatible and operate from a single 5v supply. fully asynchronous circuitry requires no clocks or refreshing for operation and provides equal access and cycle times for ease of use. the zip and simm modules contain four pd (presence detect) pins which are used to identify module memory density in applications where alternate modules can be interchanged. features 256kx32 bit cmos static random access memory ? access times bicmos: 10 and 12ns cmos: 15, 20, 25, and 35ns ? individual byte selects ? fully static, no clocks ? ttl compatible i/o high density package with jedec standard pinouts ? 72 pin simm no. 175 (angle) ? 72 pin zip no. 176 ? 72 pin simm, no. 354 (straight) single +5v (10%) supply operation pin names a?-a17 address inputs e?-e3 chip enables w, write enables g output enable dq?-dq31 common data input/output vcc power (+5v10%) vss ground pin configurations and block diagram nc pd3 vss pd2 dq8 dq9 dq10 dq11 a? a1 a2 dq12 dq13 dq14 dq15 vss a15 e1 e3 a17 g dq24 dq25 dq26 dq27 a3 a4 a5 vcc a6 dq28 dq29 dq30 dq31 nc nc nc pd4 pd1 dq? dq1 dq2 dq3 vcc a7 a8 a9 dq4 dq5 dq6 dq7 w a14 e? e2 a16 vss dq16 dq17 dq18 dq19 a10 a11 a12 a13 dq20 dq21 dq22 dq23 vss nc nc 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 w g e e1 e2 e3 dq -dq3 dq8-dq11 dq16-dq19 dq24-dq27 dq4-dq7 dq12-dq15 dq20-dq23 dq28-dq31 4 4 4 4 4 4 4 4 72 pin pd 1,2 - vss pd 3,4 - open 256kx32 static ram cmos, high speed module electronic designs incorporated ? one research drive ? westborough, ma 01581usa ? 508-366-5151 ? fax 508-836-4850 ? electronic designs europe ltd. ? shelley house, the avenue ? lightwater, surrey gu18 5rf united kingdom ? 01276 472637 ? fax: 01276 473748
EDI8F32259C 256kx32 sram module 2 EDI8F32259C rev. 1 12/97 eco #9619 absolute maximum ratings* recommended dc operating conditions (f=1.0mhz, vin=vcc or vss) parameter sym max unit address lines ci 60 pf data lines cd/q 20 pf chip enable line cc 20 pf write control line cn 60 pf these parameters are sampled, not 100% tested. ac test conditions *stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. parameter sym min typ max units supply voltage vcc 4.5 5.0 5.5 v supply voltage vss 0 0 0 v input high voltage vih 2.2 -- vcc+0.3v v input low voltage vil -0.3 -- 0.8 v (note: for tehqz,tghqz and twlqz, cl = 5pf) input pulse levels vss to 3.0v input rise and fall times 5ns input and output timing levels 1.5v output load 1ttl, cl = 30pf voltage on any pin relative to vss -0.5v to 7.0v operating temperature ta (ambient) commercial. 0c to +70c industrial -40c to +85c storage temperature, plastic -55c to +125c power dissipation 7.5 watt output current. 20 ma e w g mode output power h x x standby high z icc3 l h l read dout icc1 l l x write din icc1 l h h output deselect high z icc1 truth table capacitance dc electrical characteristics parameter sym conditions min max max max max units 10-12 15ns 20 25-35 ns operating power supply current icc1 w, e = vil, ii/o = 0ma, min cycle 1360 1280 1440 1280 ma standby (ttl) power supply current icc2 e 3 vih, vin vil or vin 3 vih 480 240 200 200 ma full standby power supply current icc3 e 3 vcc-0.2v 80 80 40 40 ma cmos vin 3 vcc-0.2v or vin 0.2v input leakage current ili vin = 0v to vcc -- 80 80 80 80 a output leakage current ilo v i/o = 0v to vcc -- 20 20 20 20 a output high voltage voh ioh = -4.0ma 2.4 v output low voltage vol iol = 8.0ma 0.4 0.4 0.4 0.4 v *typical: ta = 25c, vcc = 5.0v
EDI8F32259C 256kx32 sram module 3 EDI8F32259C rev. 1 12/97 eco #9619 ac characteristics read cycle symbol 10ns* 12ns* 15ns parameter jedec alt. min max min max min max units read cycle time tavav trc 10 12 15 ns address access time tavqv taa 10 12 15 ns chip enable access telqv tacs 10 12 15 ns chip enable to output in low z (1) telqx tclz 3 3 3 ns chip disable to output in high z (1) tehqz tchz 5 6 8 ns output hold from address change tavqx toh 3 3 3 ns output enable to output valid tglqv toe 5 5 8 ns output enable to output in low z (1) tglqx tolz 0 0 0 ns output disable to output in high z (1) tghqz tohz 4 4 5 ns read cycle 2 - w high note 1: parameter guaranteed, but not tested. *bicmos read cycle 1 - w high, g, e low tavav tavqv tavqx data 2 a q address 1 address 2 data 1 tghqz telqv telqx e g q tehqz a tavav tglqv tglqx tavqv
EDI8F32259C 256kx32 sram module 4 EDI8F32259C rev. 1 12/97 eco #9619 symbol 20ns 25ns 35ns parameter jedec alt. min max min max min max units read cycle time tavav trc 20 25 35 ns address access time tavqv taa 20 25 35 ns chip enable access telqv tacs 20 25 35 ns chip enable to output in low z (1) telqx tclz 3 3 3 ns chip disable to output in high z (1) tehqz tchz 10 12 15 ns output hold from address change tavqx toh 3 3 3 ns output enable to output valid tglqv toe 13 15 20 ns output enable to output in low z (1) tglqx tolz 0 0 0 ns output disable to output in high z(1) tghqz tohz 8 10 12 ns note 1: parameter guaranteed, but not tested. read cycle 1 - w high: g, e low read cycle 1 w high; g, e low tavav tavqv tavqx data 2 a q address 1 address 2 data 1 read cycle 2 - w high read cycle 2 w high tghqz telqv telqx e g q tehqz a tavav tglqv tglqx tavqv ac characteristics read cycle
EDI8F32259C 256kx32 sram module 5 EDI8F32259C rev. 1 12/97 eco #9619 symbol 10ns* 12ns* 15ns parameter jedec alt. min max min max min max units write cycle time tavav twc 10 12 15 ns chip enable to end of write telwh tcw 7 8 12 ns twleh tcw 7 8 10 ns address setup time tavwl tas 0 0 0 ns tavel tas 0 0 0 ns address valid to end of write tavwh taw 7 8 10 ns taveh taw 7 8 10 ns write pulse width twlwh twp 7 8 10 ns teleh twp 7 8 10 ns write recovery time twhax twr 0 0 0 ns tehax twr 0 0 0 ns data hold time twhdx tdh 3 3 3 ns tehdx tdh 3 3 3 ns write to output in high z (1) twlqz twhz 0 5 0 6 0 9 ns data to write time tdvwh tdw 5 6 7 ns tdveh tdw 5 6 7 ns output active from end of write (1) twhqx twlz 2 2 2 ns note 1: parameter guaranteed, but not tested. *bicmos symbol 20ns 25ns 35ns parameter jedec alt. min max min max min max units write cycle time tavav twc 20 25 35 ns chip enable to end of write telwh tcw 15 20 30 ns twleh tcw 15 20 30 ns address setup time tavwl tas 0 0 0 ns tavel tas 0 0 0 ns address valid to end of write tavwh taw 15 20 30 ns taveh taw 15 20 30 ns write pulse width twlwh twp 15 20 30 ns teleh twp 15 20 30 ns write recovery time twhax twr 0 0 0 ns tehax twr 0 0 0 ns data hold time twhdx tdh 3 3 3 ns tehdx tdh 3 3 3 ns write to output in high z (1) twlqz twhz 0 10 0 12 0 15 ns data to write time tdvwh tdw 12 15 20 ns tdveh tdw 12 15 20 ns output active from end of write (1) twhqx twlz 3 3 3 ns note 1: parameter guaranteed, but not tested. ac characteristics write cycle ac characteristics write cycle
EDI8F32259C 256kx32 sram module 6 EDI8F32259C rev. 1 12/97 eco #9619 a w e d q tavav tavel tehax tdveh tehdx teleh taveh data valid high z twleh write cycle 1 - w controlled write cycle 2 - e controlled a e w d q tavav telwh tavwh twlwh tavwl tdvwh twhdx twhqx high z twlqz data valid twhax
EDI8F32259C 256kx32 sram module 7 EDI8F32259C rev. 1 12/97 eco #9619 part number speed package (ns) no. bicmos edi8g32259b10mnc 10 176 edi8g32259b12mnc 12 176 cmos EDI8F32259C15mnc 15 176 EDI8F32259C20mnc 20 176 EDI8F32259C25mnc 25 176 EDI8F32259C35mnc 35 176 part number speed package (ns) no. bicmos edi8g32259b10mmc 10 354 edi8g32259b12mmc 12 354 cmos EDI8F32259C15mmc 15 354 EDI8F32259C20mmc 20 354 EDI8F32259C25mmc 25 354 EDI8F32259C35mmc 35 354 ordering information note: for gold simm, change from edi8f to edi 8g. part number speed package (ns) no. bicmos edi8g32259b10mzc 10 175 edi8g32259b12mzc 12 175 cmos EDI8F32259C15mzc 15 175 EDI8F32259C20mzc 20 175 EDI8F32259C25mzc 25 175 EDI8F32259C35mzc 35 175 package description package no. 175 72 pin zip .360 max. .100 typ. p1 .050 .050 3.865 max. .020 .100 typ. .052 typ. .250 typ. .175 .125 .590 max.
EDI8F32259C 256kx32 sram module 8 EDI8F32259C rev. 1 12/97 eco #9619 electronic designs incorporated ? one research drive ? westborough, ma 01581 usa ? 508-366-5151 ? fax 508-836-4850 ? electronic designs europe ltd. ? shelley house, the avenue ? lightwater, surrey gu18 5rf united kingdom ? 01276 472637 ? fax: 01276 473748 http://www.electronic-designs.com electronic designs inc. reserves the right to change specifications without notice. cage no. 66301 package no. 176 72 pin simm angled package no. 354 72 pin simm straight 2.045 1.992 .062 r. .125 min. max. .360 .225 min. .250 .062 r. .680 max. p1 .050 typ. 4.255 max. .250 typ. 3.750 3.984 .400 j2 j1 j4 r.# p1 .250 .400 .600 max. .250 typ. .050 typ. 3.750 2.045 1.992 .062 r. (2x) .125 dia (2x) 3.984 .125 min. .360 max. 4.255 max 164
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